1. Field of the Invention
This invention is related to storage arrays, essentially static random access memories (SRAMs) and more particularly to precharging bitlines (BL) to sub-VDD levels.
2. Description of Background
High performance low power SRAM design including multiple local cell groups are well known in the prior art including for example U.S. Pat. Nos. 5,668,761 and 6,657,886. Each cell group includes multiple local cell and local true and complements bitlines. Each SRAM cell includes a pair of inverters that operate together in a loop to store true and complement data. However, competing requirements of Read and Write margin improvements on the SRAM cell design limit the scalability of cell transistor dimensions and operating voltages in a conventional cell and static power supplies. These patents did not employ pre-charging bitlines to sub-VDD levels. During a read operation, SRAM Bitlines are typically precharged to a full VDD level. Charge injection from the VDD-precharged Bitlines into the cell node with the “0” level stored in the cell, causes the cell node to rise above the GND level. If the rise of the “0” level on the Low-side of the cell reaches the trip-point of the feedback inverter of the cell (driving the “1” side of the cell), the data in the cell can be flipped, and therefore, corrupted. Therefore, precharging bitlines to a sub-VDD level will decrease the charge injection into the cell and improve the stability margin of the cell.
Precharging Bitlines to sub-VDD level has been done by M. Khellah, et. al. in VLSI 2006 (pg. 12-13) which is hereby included in its entirety herein. It describes a method for briefly pulsing Bitlines towards GND before Wordline activation which is shown in FIG. 1. This solution provides a stability benefit at a cost of cycle time. This is because the precharge pulse has to occur before Wordline activation, which directly impacts access time and cycle time. Furthermore, the discharge level of the Bitline is poorly controlled. The pulse width of the device controlling the GND-connected devices (MD/MDC) has to be precisely timed. Any variations of this pulse width have to be calibrated with the variations of the GND-connected devices. For example, if the pulse width is too wide, then the bitlines are precharged to a level which is too low to provide the stability margin. Precharging below the optimum level will cause further degrade in the stability margins.
Bhavnagarwala, et. al. in 2007 Symposium on VLSI Digest of Technical Papers (pg. 78-79) which is hereby included in its entirety herein describes and shows an NFET source follower that is used to precharge Bitlines to sub-VDD level. As illustrated in FIG. 2 the gate of the NFET precharge device is externally controlled at Vb to allow the user to change the level of Bitline precharge voltage. It has been known for large signal sensing schemes that a lower BL precharge voltage directly translates into larger stability margin. For such a design the Vb is driven from the pad having a DC signal, The DC signal is controlled external to the memory to allow the user to change the level of the precharge voltage. This design is simple and it provides a low risk addition to POR circuitry. There are two drawbacks to this design. One drawback is that the source follower NFET design has a very limited conduction range. When precharge occurs, the source follower NFET can quickly precharge bitlines to about VDD/2. From VDD/2 to the final precharge level (approximately VDD-Vtn), the overdrive of the NFET quickly decreases as its SOURCE is raised towards VDD-Vtn, which weakens the device, increases the slew rate of the bitline precharge, and degrades the cycle time. Another drawback of this design is that the precharge level can have large variations based on the Process, Voltage, and Temperature (PVT) of operation. This PVT variation will result in large variations of the Vt of the device and therefore, precharge levels on the bitline.